Electrically-erasable, electrically-programmable, read-only memories typically consist of an array of MOSFETs with a floating gate in the case of a double poly structure or with NMOS in the case of a single poly structure. In the case of the double poly floating gate structure, a typical cell consists of a substrate of a specified conductivity type with two heavily doped regions of an opposite conductivity type formed in its face. The heavily doped regions, designated the drain and the source, are separated by a field effect transistor channel region. A thin oxide layer is grown on the surface of the channel and a floating gate is then formed on the oxide. A control gate, separated from floating gate by another layer of oxide, is formed so as to be capacitively coupled thereto upon the application of a control gate voltage.
In the case of the double poly floating gate structure, each EEPROM cell stores a bit of information as a quantity of electrons on the floating gate. A charged floating gate raises the threshold voltage of the MOS field effect transistor preventing current flow through the channel when a reading voltage difference is established between the drain and the source, thereby storing a logic "zero". An uncharged floating gate does not alter the threshold voltage of the channel of the field effect transistor, and therefore a normal data reading voltage applied to the control gate will exceed the threshold voltage such that current will pass through the channel when a voltage difference is established between the drain and the source, thereby storing a logic "one".
One category of double poly floating gate EEPROM cells employs only a single relatively low voltage supply for all and the programming, erasing and reading operations. Programming and erasing are accomplished by Fowler-Nordheim tunneling through a thin dielectric tunneling window. To program a cell, a relatively high voltage (typically on the order of +18 volts) is applied to the control gate while the source/drain region adjacent the thin tunneling window is held at a low voltage (typically zero volts or ground). The resulting difference in voltage between the floating gate and the source/drain region adjacent the tunneling window causes electrons to tunnel across the silicon dioxide barrier. To erase a selected cell, a relatively high voltage (typically on the order of +18 volts) is applied to the source/drain region adjacent the tunneling window while a low voltage (typically zero volts or ground) is applied to the control gate. In this case, the resulting voltage difference between the source/drain region and the floating gate causes electrons to tunnel from the floating gate to the source/drain region across the thin oxide tunnelling window.
A full featured EEPROM can be programmed and erased cell by cell, or in groups of cells. This is in contrast to "flash" erasable EEPROM cells in which the entire array is typically erased at once. Full featured EEPROM include one select field effect transistor and one field effect transistor with a floating gate structure (the memory transistor). Currently available full featured EEPROMS which include a thin oxide tunnelling window for programming and erasing are large because the minimum geometry of the tunnelling windows has been limited by the available manufacturing processes. This presents significant disadvantages for memory designers. A smaller cell size is desirable in order to provide a more dense memory array with more EEPROM cells for a given silicon area. Further, smaller cell size reduces the manufacturing costs and increases manufacturing yields.
Thus, the need has arisen for a full featured EEPROM cell with reduced cell size, an array of such cells and methods for making and using the same.